With continued pressure to make increasingly dense devices, the semiconductor device industry is switching to the use of 3D memory structures. For instance, NAND flash memory has moved from a planar configuration to a vertical configuration (VNAND). This vertical configuration permits the memory devices to be formed at significantly greater bit density. One operation involved in formation of VNAND devices involves etching holes into a stack of alternating layers of materials. As the stacks of alternating layers of materials grow to include larger numbers of layers, this etching operation becomes increasingly difficult.